This application is based upon and claims priority of Japanese Patent Application No. 11-041785 filed on Feb. 19, 1999, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a packet buffer device and a packet assembling method in a packet transfer module which assembles logical channel-multiplexed asynchronous transfer mode (ATM) cells into packets and stores and outputs the cells in packet units. More particularly, the present invention relates to a packet buffer device and a packet assembling method in a packet transfer module for a mixed network including best effort-type packet transfer services using a common buffer, and guaranteed-type packet transfer services (bandwidth guarantee) using discrete buffers.
2. Description of the Related Art
FIG. 1 is a diagram illustrating the location of network installation of packet transfer modules in an ATM network. As shown in FIG. 1, the packet transfer modules 24-1 installed in the ATM network are connected to one another, and are connected to user network routers 24-3 via multiplexing devices 24-2.
Individual packet transfer modules 24-1, multiplexing devices 24-2, and routers 24-3 are connected by an asynchronous transfer mode interface. Individual packets sent from a user network are converted to ATM cells by a router 24-3 using an ATM adaptation layer type 5 (referred to hereinafter as xe2x80x9cAAL-type 5xe2x80x9d) or other such protocol. The multiplexing devices 24-2 perform multiplexing of ATM cells for multiple users and provide the multiplexed ATM cells to respective packet transfer modules 24-1.
The respective packet transfer modules 24-1 assemble packets from ATM cells and transfer packets to another packet transfer module 24-1 accommodated in a remote destination user network or to a remote destination user network accommodated in the same packet transfer module 24-1 according to remote destination address information within a packet header.
FIG. 2 is a block diagram of a packet transfer module 25-10. As shown in FIG. 2, ATM cells multiplexed into logical channel units are input from another packet transfer module or multiplexing device to the packet transfer module 25-10 via a circuit. A logical channel is a channel identified by a virtual channel identifier (VPI/VCI) or the like.
The packet transfer module 25-10 includes a physical terminal device 25-11 to perform physical layer termination of the ATM cell input/output, an ATM terminal device 25-12 to perform ATM layer termination of ATM cell input/output, and an AAL-type 5 terminal device 25-13 to perform AAL-type 5 termination of ATM cell input/output. The AAL-type 5 terminal device 25-13 may also be another ATM adaptation layer-type terminal device, such as a type 3 or type 4 termination device.
A packet buffer device 25-14 identifies an ATM cell, which is a packet end data for each logical channel, based on payload-type indication information in the ATM cell header and according to AAL-type 5 flow control or the like. The packet buffer device 25-14 assembles a packet from ATM cells received up to that point. Packet header information including a remote destination address or the like is then output to an upper layer device 25-15.
The upper layer device 25-15 searches an input packet for a transfer destination and transmits the result of the search for a transfer destination to the packet buffer device 25-14. The packet buffer device 25-14 converts a transfer destination designated by the upper layer device 25-15 to a logical channel and outputs, in packet units, ATM cells assembled into packets.
A packet transfer module controller 25-16 performs initial setting, status control and the like of each device in the packet transfer module 25-10. ATM cells output from the packet transfer module 25-10 are multiplexed into packet units and output in this form.
A conventional packet buffer device uses two types of buffering methods. One type of buffering method is to use a common buffer which stores, in a single common buffer resource, ATM cells from all subscribers to which a logical channel is assigned. Another type of buffering method is to use a conventional packet buffer device comprising discrete buffers which store ATM cells from individual subscribers in discrete buffer resources having fixed capacity previously assigned to each individual logical channel
FIG. 3 is a diagram illustrating the operation of a packet buffer device using a common buffer. As shown in FIG. 3, when a plurality of logical channel-multiplexed ATM cells corresponding to channels A, B, C, and D are input, the packet buffer device stores the plurality of ATM cells in packet units in a buffer memory 26-1 which is commonly assigned to individual logical channels.
When many ATM cells corresponding to channel A are input to the common buffer memory 26-1 so that the amount of channel A buffer memory used increases and there is insufficient empty capacity in the buffer memory 26-1, packets corresponding to another channel, such as channel D, are abandoned.
FIG. 4 is a diagram illustrating the operation of a packet buffer device using discrete buffers. As shown in FIG. 4, when a plurality of logical channel-multiplexed ATM cells corresponding to channels A, B, and C are input, the packet buffer device stores the several ATM cells in discrete buffers within a buffer memory 27-1, which discrete buffers are dedicated respectively to channel A, B, C, D and E use.
In a packet buffer device using discrete buffers, congestion among channels has no mutual effect. For example, as shown in FIG. 4, even though discrete buffers for channel D and channel E are empty, if the discrete buffers for channel A and channel B converge, packets from these channels will be abandoned.
In a packet buffer device using a common buffer, buffer processing during buffer congestion does not distinguish between packets associated with high priority, guaranteed-type transfer service, and packets associated with low-priority, best effort-type packet transfer service. Thus, it is not possible to effect abandonment processing that discriminates according to transfer service grades.
On the other hand, a packet buffer device using discrete buffers is problematic in that, if there is insufficient capacity in a certain discrete buffer resource, packets corresponding to the discrete buffer with insufficient buffer capacity are abandoned even though there is capacity in another discrete buffer resource. As a result, buffer resources are not used effectively and best effort-type packet transfer service cannot be provided with good efficiency.
Recently, ATM networks transferring Internet Protocol (IP) packets and the like have seen a transition to high speeds and high-level multiplexing, as well as a further proliferation of transfer service grades. The response to such packet transfer services requires packet buffer devices which use buffer resources optimally and which also use buffer resources selectively according to transfer service grade.
It is an object of the present invention to provide a method and apparatus for dynamically constructing common buffers and discrete buffers.
Another object of the present invention is to provide a method and apparatus for optimally assigning the buffer capacity of both a common buffer type and a discrete buffer type to achieve optimal use of buffer resources.
A further object of the present invention is to provide a packet transfer service corresponding to a service mode such that packets associated with different service mode subscribers are selectively apportioned to buffers differing according to individual service mode type, even in an instance wherein the subscribers accommodated are a mixture of differing service mode subscribers.
Objects and advantages of the present invention are achieved in accordance with embodiments of the present invention with a packet buffer device to store ATM cells multiplexed and input via multiple logical channels, and to assemble ATM cells corresponding to each logical channel into packets in a buffer, comprising a discrete buffer controller to generate a discrete buffer from a common buffer; a buffer type determination unit to determine a buffer type to store an ATM cell for each input ATM cell; and a packet buffer controller to assign the ATM cell to the common buffer or to the discrete buffer, according to the buffer type.
In accordance with the present invention, the discrete buffer controller releases the discrete buffer to the common buffer after outputting the assembled packet.
In accordance with embodiments of the present invention, the buffer type determination unit further comprises a target logical channel setting unit to set a correspondence between buffer type information designating a discrete buffer or a common buffer and an ATM cell logical channel; and a comparator to compare the logical channel of an input ATM cell and the ATM cell logical channel, and to output the buffer type information corresponding to the logical channel of the input ATM cell.
In accordance with the present invention, the target logical channel setting unit includes bit designation information to designate a logical channel determination target bit set for each discrete buffer type, and the comparator compares a logical channel determination target bit for an input ATM cell to the logical channel determination target bit designated by the bit designation information, and outputs the buffer type information designating a discrete buffer type when there is a match, or buffer type information designating a common buffer when there is not a match.
In accordance with embodiments of the present invention, the target logical channel setting unit includes priority degree information to indicate the degree of priority of an ATM cell or a packet for each discrete buffer type, and wherein the comparator compares information indicating the priority degree of an input ATM cell or a packet and priority degree information indicating the degree of priority, and outputs the buffer type information according to the comparison results.
In accordance with embodiments of the present invention, the packet buffer device further comprises an empty buffer pointer, for each buffer type, to hold an empty buffer leading pointer linking empty buffers in a chain, and an empty buffer count; and a buffer management unit, for each buffer, to hold a buffer type, and a next address of an empty buffer linked in a chain, wherein the packet buffer controller sequentially acquires buffers from the empty buffer indicated by the empty buffer leading pointer according to buffer type information from the buffer type determination unit, and controls packet assembly.
In accordance with the present invention, the packet buffer controller reads the empty buffer count held in the empty buffer pointer corresponding to the discrete buffer type in response to acquiring a discrete buffer, acquires a buffer from an empty buffer of a common buffer in response to determining that there is no empty discrete buffer to acquire, and performs control of packet assembly.
In accordance with embodiments of the present invention, the packet buffer controller further comprises a device to assess a discrete buffer increase indication from the discrete buffer controller, to rewrite a buffer type held within the buffer management unit corresponding to a buffer acquired from an empty buffer of a common buffer to a buffer type designating a relevant discrete buffer in response to the discrete buffer increase indication, and to modify several buffers acquired from a common buffer to discrete buffers.
In accordance with embodiments of the present invention, the packet buffer device may further comprise a buffer management unit to hold a buffer type for each buffer, and the discrete buffer controller may further comprise a discrete buffer total designation unit to designate a discrete buffer total for each buffer type; a buffer counter to count discrete buffers; a buffer construction indication unit to indicate buffer construction; and a management unit to rewrite the buffer type of the buffer within the buffer management unit to a discrete buffer type, during buffer release processing following ATM cell output, when the buffer is a common buffer and a buffer construction indication is present in the buffer construction indication unit, to increase the buffer counter, and to turn off the buffer construction indication when the buffer counter reaches the discrete buffer total.
In accordance with embodiments of the present invention, the discrete buffer controller further comprises a buffer release indication unit to indicate buffer release, and the management unit rewrites the buffer type of the buffer within the buffer management unit to a common buffer type during buffer release processing following ATM cell output when the buffer is a discrete buffer and a buffer release indication is present in the buffer release indication unit, decreases the buffer count, and turns off the buffer release indication when the buffer count reaches the discrete buffer total.
In accordance with embodiments of the present invention, the packet buffer device further comprises a discrete empty buffer pointer to hold an empty buffer leading pointer linking empty buffers in a chain, and an empty buffer count; and an empty buffer count minimum value storage unit to store a minimum value corresponding to the empty buffer count, and the discrete buffer controller further comprises an adjustment interval timer to set a period for optimization processing of the number of discrete buffers; and wherein the management unit reads the empty buffer count minimum value at a period set by the adjustment interval timer, subtracts the empty buffer count minimum value from a value read from the discrete buffer total designation unit, sets the subtracted value in the discrete buffer total designation unit, and turns on the buffer release indication.
In accordance with embodiments of the present invention, the packet buffer device further comprises a discrete empty buffer pointer to hold an empty buffer leading pointer linking empty buffers in a chain, and an empty buffer count; and an empty buffer count minimum value storage unit to store a minimum value corresponding to the empty buffer count, and the discrete buffer controller further comprises an adjustment interval timer to set a period for optimization processing of the number of discrete buffers; a threshold value setting unit to set a threshold value for the empty buffer count minimum value in order to determine whether or not to perform optimization processing of the number of discrete buffers; and a release count designation unit to set a number of buffers to release, wherein the management unit reads the empty buffer count minimum value at a period set by the adjustment interval timer, subtracts the setting in the release count designation unit from the discrete buffer total when the empty buffer count minimum value read is larger than the threshold value, sets the subtracted value in the discrete buffer total designation unit, and turns on the buffer release indication.
Objects and advantages of the present invention are achieved in accordance with embodiments of the present invention with a packet buffer device to store ATM cells multiplexed and input via multiple logical channels, and to assemble ATM cells pertaining to each logical channel into packets in a buffer, comprising a determining device to determine a buffer type to store an ATM cell for each input ATM cell; and an assigning device to assign the ATM cell according to the buffer type, to a common buffer or a discrete buffer according to the buffer type.
In accordance with embodiments of the present invention, the assigning device assigns an ATM cell whose buffer type is a discrete buffer type to the common buffer when there is no discrete buffer.
The packet buffer device in accordance with embodiments of the present invention may further comprise a changing device to change a number of common buffer or a number of discrete buffer dynamically in response to a condition.
In accordance with embodiments of the present invention, the common buffer is assigned to commonly store ATM cells corresponding to each logical channel, and the discrete buffer is assigned to store ATM cells corresponding to a specified logical channel.
Objects and advantages of the present invention are achieved in accordance with embodiments of the present invention with packet assembling method for assembling ATM cells multiplexed and input via multiple logical channels into packets, comprising determining a buffer type in which to store an ATM cell for each input ATM cell; and assigning the ATM cell to a common buffer or a discrete buffer according to the buffer type determination.
In accordance with the present invention, the packet assembling method further comprises assigning the ATM cell whose buffer type is a discrete buffer type to the common buffer when there is no discrete buffer.
In accordance with embodiments of the present invention, the packet assembling method further comprises changing a number of common buffer or a number of discrete buffer dynamically in response to a condition.
Thus, the packet buffer device in accordance with embodiments of the present invention can dynamically construct a discrete buffer according to the number of discrete buffers used, and can allocate buffer resources of differing type according to packet type.
Further, the packet buffer device in accordance with embodiments of the present invention can apportion the logical channel ATM cells set by the target logical channel setting unit to differing types of discrete buffers.
In accordance with the present invention, cell loss priority indication (CLP) for an ATM cell or IPv6 packet priority information may also be used as the information indicating priority.
Moreover, the packet buffer device in accordance with embodiments of the present invention can increase discrete buffers to the generated or designated discrete buffer count corresponding to the designated buffer total at buffer release.
Furthermore, the packet buffer device in accordance with embodiments of the present invention can decrease discrete buffers to the released or designated discrete buffer total at buffer release.
Further, the packet buffer device in accordance with embodiments of the present invention can release the number of discrete buffers not used in the duration of the optimization processing period to the common buffer.
Moreover, the packet buffer device in accordance with embodiments of the present invention can release the designated number of buffers set in the release count designation unit to a common buffer when the number not used in the duration of the optimization processing period is larger than the threshold value.